IRFD113, sihfd113 www.vishay.com vishay siliconix s11-2479-rev. a, 19-dec-11 1 document number: 91487 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power mosfet features ? for automatic insertion ? compact plastic package ?end stackable ? fast switching ? low drive current ? easily paralleled ? excellent temperature stability ? compliant to rohs directive 2002/95/ec note * pb containing terminations are not rohs compliant, exemptions may apply description the hvmdip technology is the key to vishays advanced line of power mosfet transistors. the efficient geometry and unique processing of the hvmdip design achieves very low on-state resistance combined with high transconductance and extreme device ruggedness. hvmdips feature all of the established advantages of mosfets such as voltage control, very fast switching, ease of paralleling, and temperature stability of the electrical parameters. the hvmdip 4 pin, dual-in-line package brings the advantages of hvmdips to high volume applications where automatic pc board insertion is desireable, such as circuit boards for computers, print ers, telecommunications equipment, and consumer produ cts. their compatibility with automatic insertion equipment, low-profile and end stackable features represent the stat-of-the-art in power device packaging. notes a. t j = 25 c to 150 c b. repetitive rating; puls e width limited by maximum junction temperature. c. 1.6 mm from case. product summary v ds (v) 60 r ds(on) ( )v gs = 10 v 0.8 q g (max.) (nc) 7 q gs (nc) 2 q gd (nc) 7 configuration single n-channel mosfet g d s hvmdip d s g ordering information package hvmdip lead (pb)-free IRFD113pbf sihfd113-e3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage a v ds 60 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 0.8 a pulsed drain current b i dm 6.4 linear dera ting factor 0.008 w/c inductive current, clamped l = 100 h i lm 6.4 a maximum power dissipation t c = 25 c p d 1.0 w operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (peak temperature) for 10 s 300 c
IRFD113, sihfd113 www.vishay.com vishay siliconix s11-2479-rev. a, 19-dec-11 2 document number: 91487 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. repetitive rating; pu lse width limited by maximum junction temperature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja - 120 c/w specifications (t c = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 60 - - v gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 gate-source leakage i gss v gs = 20 v - - 500 na zero gate voltage drain current i dss v ds = max. rating, v gs = 0 v - - 250 a v ds = max. rating x 0.8, v gs = 0 v, t c = 125 c - - 1000 on-state drain current b i d(on) v gs = 10 v v ds > i d(on) x r ds(on) max. 0.8 - - a drain-source on-state resistance b r ds(on) v gs = 10 v i d = 0.8 a - 0.6 0.8 forward transconductance b g fs v ds > i d(on) x r ds(on) max., i d = 0.8 a 0.8 1.2 - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz - 135 200 pf output capacitance c oss -80100 reverse transfer capacitance c rss -2025 total gate charge q g v gs = 10 v i d = 4 a, v ds = 0.8 max. rating -57 nc gate-source charge q gs -2- gate-drain charge q gd -7- turn-on delay time t d(on) v dd = 0.5 v ds , i d = 0.8 a, r g = 50 -1020 ns rise time t r -1525 turn-off delay time t d(off) -1525 fall time t f -1020 internal drain inductance l d between lead, 2 mm (0.08") from package and center of die contact -4.0- nh internal source inductance l s -6.0- drain-source body diode characteristics continuous source-dra in diode current i s mosfet symbol showing the integral reverse p - n junction diode --0.8 a pulsed diode forward current i sm --6.4 body diode voltage a v sd t a = 25 c, i s = 0.8 a, v gs = 0 v - - 2 v body diode reverse recovery time t rr t j = 150 c, i f = 1.0 a, di/dt = 100 a/s - 100 - ns body diode reverse recovery charge q rr -0.2-c forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g
IRFD113, sihfd113 www.vishay.com vishay siliconix s11-2479-rev. a, 19-dec-11 3 document number: 91487 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical transfer characteristics fig. 3 - typical saturation characteristics fig. 4 - maximum sa fe operatung area
IRFD113, sihfd113 www.vishay.com vishay siliconix s11-2479-rev. a, 19-dec-11 4 document number: 91487 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 5 - typical transconductance vs. drain current fig. 6 - typical source-dra in diode forward voltage fig. 7 - breakdown voltage vs. temperature fig. 8 - normalized on-resistance vs. temperature
IRFD113, sihfd113 www.vishay.com vishay siliconix s11-2479-rev. a, 19-dec-11 5 document number: 91487 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 9 - typical capacitance vs. drain-to-source voltage fig. 10 - typical gate charge vs. gate-to-source voltage fig. 11 - typical on-res istance vs. darin current fig. 12 - maximum darin current vs. case temperature
IRFD113, sihfd113 www.vishay.com vishay siliconix s11-2479-rev. a, 19-dec-11 6 document number: 91487 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 13 - power vs. temperature derating fig. 14 - clamped inductive test circuit fig. 15 - clamped inductive waveforms fig. 16 - switching time test circuit fig. 17 - gate charge test circuit fig. 18 - typical time to ac cumulated 1 % gate failure fig. 19 - typical high temperature reverse bias (htrb) failure rate i p e c v d s v dd i l
IRFD113, sihfd113 www.vishay.com vishay siliconix s11-2479-rev. a, 19-dec-11 7 document number: 91487 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 20 - for n-channel vishay siliconix maintains worldwide manufactu ring capability. products may be manufact ured at one of seve ral qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91487 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd
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